Certain widely-used semiconductor device packages having high lead counts, such as thin small outline plastic packages (TSOPs), side small outline plasctic packages (SSOPs), pin grid arrays (PGAs), ball grid arrays (BGAs), etc. are typically loaded into trays for shipping to customers and for in-process handling or transport (e.g. for shipping to a test facility from a packaging facility). The trays protect the packages from electrical and mechanical damage during handling and shipment, and are also suitable for presenting the packages to processing equipment, such as test stations and circuit board assembly equipment. Trays are usually made of a polymer, such as polyvinylchloride (PVC), either carbon-filled or antistatically coated to provide electrostatic discharge (ESD) protection.
The trays are typically uniformly sized, in compliance with standard JEDEC outlines, and have an internal configuration to prevent excess motion of the package within the tray and to orient the package in a JEDEC standard way (e.g., "pin one orientation") to enable pick-and-place equipment to be compatible with all the packages. An example of a typical tray is depicted in FIG. 1, wherein five trays 100 are stacked for shipment, with a sixth tray 100 serving as a cover. Conventionally, a different tray is required for each specific package design. As a result, there are at least hundreds of different tray types in use. This requirement of a customized tray for each new package design is disadvantageous because customized trays are costly, and each new tray design typically has a long lead time associated with its development and manufacture. Since a new product cannot be shipped to customers or test facilities without a proper tray, tray customization undesirably increases the time to market for a new package design.
There exists a need for a shipping tray for packaged semiconductor devices that is usable with more than one package design, thereby reducing manufacturing costs and decreasing the time to market for new package designs.